Arm Strikes to Accelerate IoT Development With Virtual Hardware Platform

Arm Strikes to Accelerate IoT Development With Virtual Hardware Platform

From start to finish, device development can take years. Hoping to accelerate the process for IoT devices specifically comes Arm Total Solutions’ Virtual Hardware and Project Centauri.
Being a multidisciplinary field, the Internet of Things (IoT) requires immense amounts of collaboration in the development cycle of a product. OEMs, silicon designers, and software developers must deal with requirements such as connectivity, security, and the rapid evolution of machine learning (ML), creating complex requirements that hinder the IoT development process.
This week, in an attempt to decrease IoT devices’ time to market, Arm has announced Arm Total Solutions. As a whole, Total Solutions is an initiative to accelerate IoT product development by supplying engineers with reference code, machine learning models, hardware IP, and virtual development platforms. Within Total Solutions are two significant tenants: Virtual Hardware and Project Centauri.

Arm’s roadmap for IoT. Image used courtesy of Arm

This article will briefly cover each initiative and how Arm believes they can help push IoT forward.

IoT Challenges
One of the biggest challenges in the development lifecycle of an IoT device is that hardware and software development, for the most part, cannot be done in parallel.
Before the software team can start developing applications such as ML models for their specific hardware, the hardware itself needs to exist already. The development of the hardware itself, of course, is a lengthy and arduous process in itself. From ideation to completion, the hardware product lifecycle can take years, consisting of countless revisions, design reviews, tests, and design for manufacturing.
In the interim, it is difficult for a software developer to be fully productive. They can use development kits to get their software off the ground, but it isn’t easy to get software fully developed without access to the product-specific hardware and all of its quirks.

Virtual Hardware
This week, Arm is challenging this narrative with the release of Arm Virtual Hardware.

Traditional versus Virtual Hardware’s software development flow. Image used courtesy of Arm

Arm’s Virtual Hardware is a new, cloud-based development platform that provides functionally accurate models of Arm-based SoCs for application developers to build and test software with before and after silicon and hardware availability. The platform runs in the cloud, simulating hardware dependencies, including memory and peripherals, which allow the software team to develop on realistic models.
Built with a significant focus on ML development, Virtual Hardware is optimized to allow developers to experiment, test, and iterate on different ML network configurations in a way that is much quicker than with traditional hardware.
Now let’s dive into Arm’s other main focus: Project Centauri.

Project Centauri
Along with Virtual Hardware, Total Solutions introduces Project Centauri.
Project Centauri is a new ecosystem that provides a set of device and platform standards and reference implementations for device boot, security, and cloud integration for the Arm Cortex-M.

The major offerings of Project Centauri. Image used courtesy of Arm

The major offerings of Project Centauri include foundational standards, such as cloud service-to-device specifications and common cryptographic service provider (CSP) middleware interfaces, as well as secure device management such as secure provisioning and OTA updates.
The hope for Project Centauri is that it will help drive the standards and frameworks required to scale IoT innovation in software.

Accelerating IoT
The increasing demand and complexity for IoT greatly hinder the development of products on the design side.
Arm hopes to expedite this process through the introduction of Total Solutions. Consisting of Virtual Hardware and Project Centauri, Total Solutions, which is currently in beta testing, looks to be a promising step forward.
It will be exciting to see if these initiatives take off, especially if they can back up their claims with accelerating IoT design times.

A Review of the Inverter or NOT Circuit
An inverter circuit reverses or complements the logic state applied to its input. Inversion is also termed the NOT operation.
The electromechanical circuit in Figure 1 – a battery-powered LED – shows how a NOT circuit operates. The solenoid R controls the normally closed switch a.

Figure 1. An electromechanical inverter or NOT circuit.

Initially, the only input to this circuit, A, has no connection to the battery, meaning a logic 0 signal (assuming positive logic). Under this condition, Y = 1 (logic 1), and the LED is on.
Connecting the battery to input A means logic 1. In this case, the battery energizes the solenoid R, which opens the switch a, blocking the current and turning the LED off. Under this condition, Y = 0 (logic 0).
Table 1 summarizes these results in a truth table.

A Y
0 1
1 0
Table 1. The truth table for a NOT circuit.
Figure 2 shows the logic symbol and Boolean expression for the inverter or NOT gate.

Figure 2. The logic symbol and Boolean expression for the inverter or NOT gate.

The NAND Gate
NAND stands for NOT-AND. A NAND gate is an AND gate followed by a NOT circuit – a negated output. This is one of the most useful combinations of gates.
Figure 3 is an electromechanical circuit showing the principle of a NAND gate.

Figure 3. An electromechanical NAND circuit.

The battery supplies power to the LED through the normally closed switches a and b. The solenoid R1 controls switch a, and the solenoid R2 controls switch b.
Initially, inputs A and B are de-energized, meaning a logic 0 signal (assuming positive logic). Under this condition, the LED is on and Y = 1 (logic 1).
Connecting only the input A to the battery (logic 1), the solenoid R1 opens switch a, but the LED is still supplied through switch b and Y = 1 (logic 1).
Connecting only the input B to the battery (logic 1), the solenoid R2 opens switch b, but the LED is still supplied through switch a and Y = 1 (logic 1).
Finally, connecting both inputs, A and B (logic 1), the solenoids R1 and R2 open switches a and b, de-energizing the LED. Under this condition, the LED is off and Y = 0 (logic 0).
Table 2 summarizes these results in a truth table.

A B Y
0 0 1
0 1 1
1 0 1
1 1 0
Table 2. The truth table for a two-input NAND circuit.

The output of a NAND gate is a logic 0 when all its inputs are logic 1. For all other input combinations, the result is logic 1.

The NAND Gate Symbol and Boolean Expression
Figure 4 shows the circuit symbol and Boolean expression for a two-input NAND gate.

Figure 4. Two-input NAND gate symbol and Boolean expression.

The Boolean expression for a NAND gate with more than two inputs is
Y=¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ABCDY=ABCD¯

Using a Combination of NAND Gates to Create Other Basic Logic Gates
Any logical function can be implemented by repeated use of the NAND circuit alone. Some examples follow.
Figure 5 shows a two-input NAND gate connected to create a NOT circuit. A single-input NAND is a NOT.

Figure 5. A NOT circuit made with a two-input NAND gate.

Figure 6 shows two NAND gates connected to create a two-input AND gate.

Figure 6. A two-input AND gate made with two NAND gates.

Figure 7 shows three NAND gates connected to build a two-input OR gate.

Figure 7. A two-input OR gate made with three NAND gates.

The NOR Gate
A negation following an OR is a NOT-OR or NOR gate.
Figure 8 is an electromechanical circuit showing the principle of a NOR gate.

Figure 8. An electromechanical NOR circuit.

The battery supplies power to the LED through the normally closed switches a and b. The solenoid R1 controls switch a, and the solenoid R2 controls switch b.
Initially, inputs A and B are de-energized, meaning a logic 0 signal (assuming positive logic). Under this condition, the LED is on and Y = 1 (logic 1).
Connecting only the input A to the battery (logic 1), the solenoid R1 opens switch a, blocking the current and turning the LED off. Under this condition Y = 0 (logic 0).
Connecting only the input B to the battery (logic 1), the solenoid R2 opens switch b, blocking the current and turning the LED off. Under this condition Y = 0 (logic 0).
Finally, connecting both inputs, A and B (logic 1), the solenoids R1 and R2 open switches a and b, de-energizing the LED. Under this condition, the LED is off and Y = 0 (logic 0).
Table 3 summarizes these results in a truth table.

A B Y
0 0 1
0 1 0
1 0 0
1 1 0
Table 3. The truth table for a two-input NOR circuit.

The output of a NOR gate is logic 1 when all its inputs are logic 0. For all other input combinations, the outcome is a logic 0.

The NOR Gate Symbol and Boolean Expression
Figure 9 shows the logic symbol and Boolean expression for the NOR gate.

Figure 9. Two-input NOR gate symbol and Boolean expression.

Using a Combination of NOR Gates to Create Other Basic Logic Gates
All logic can be accomplished via the NOR circuit only. Some examples follow.
Figure 10 shows a two-input NOR gate connected to produce a NOT circuit. A single-input NOR is a NOT.

Figure 10. A NOT circuit made with a two-input NOR gate.

Figure 11 shows two NOR gates connected to create a two-input OR gate.

Figure 11. A two-input OR gate made with two NOR gates.

Figure 12 shows three NOR gates connected to build a two-input AND gate.

Figure 12. A two-input AND gate made with three NOR gates.

The Inhibit (Enable) Operation
This operation is functional when the transit of a logic signal needs to be either inhibited or enabled depending upon specific control inputs.
The circuit in figure 13 – a battery powering a LED – shows the working principle of the inhibit (enable) operation.

Figure 13. The inhibit (enable) operation.

The switch denoted A is normally open, and the switch marked Ā is normally closed. Pushing switch A will turn on the LED. However, when pushing the switch Ā, the circuit opens, and the LED cannot turn on when pushing both switches simultaneously. In this way, the switch Ā has an inhibit function in which A AND Ā = 0. Using the logical connection of the AND function, it can be expressed as A ∙ Ā = 0 (or A Ā = 0).
Table 4 is the truth table for this circuit (do nothing = logic 0, push switch = logic 1, Y = 0 LED off, Y= 1 LED on).

A Ā Y
0 0 0
1 0 1
0 1 0
1 1 0
Table 4. The truth table for the circuit in figure 13.

The Inhibit Symbol and Boolean Expression
The inhibit function can be implemented by adding an additional input to an AND gate. This additional input is negated by an inverter. The NOT circuit preceding the terminal S of the AND gate acts as an inhibitor.
Figure 14 shows the logic symbol and Boolean expression for an AND gate with an enable terminal (S).

Figure 14. AND gate and Boolean expression with an enable terminal (S).

This circuit operates in accordance with the following logical statement: If A = 1, B = 1, …, M = 1, then Y = 1 provided that S = 0. A value of S = 1 forces the output to be at logic low Y = 0.
The Boolean equation reads: Y equals A AND B AND … AND M AND NOT S.
Table 5 shows the truth table for a three-input AND gate containing one inhibitor terminal (S). The enabling bit S = 0 lets the gate execute its AND logic, while the inhibiting bit S = 1 keeps the output at Y = 0, no matter what the values of the input bits are.

A B S Y
0 0 0 0
0 1 0 0
1 0 0 0
1 1 0 1
0 0 1 0
0 1 1 0
1 0 1 0
1 1 1 0
Table 5. The truth table for a three-input AND gate, with one inhibitor terminal.

About Universal Gates
It is feasible to perform any Boolean expression using either only NAND gates or only NOR gates. For this reason, the NAND and NOR are universal gates.
The NAND and NOR gates are complements of the AND and OR gates. Their truth tables are the output states of the originals but reversed.
The circuit symbols are the same but with a small circle on the output, indicating the inversion of the logic level.
The Boolean symbols change by placing a bar over the original expression: AB becomes ¯¯¯¯¯¯¯¯ABAB¯, A + B becomes ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯A+BA+B¯, and so on.
Adding a negated input to an AND gate can create the inhibit/enable functionality.

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